Field of the Invention
The application relates in general to a semiconductor device, in particular to a method for erasing NAND-type or NOR-type flash memory.
Description of the Related Art
The programming of a flash memory can allow electrons to accumulate in the floating gate, which shifts the threshold voltage of the memory cell in the positive direction. On the other hand, erasing is meant to release electrons from the floating gate, which shifts the threshold voltage of the memory cell in the negative direction. A typical erase method for a NAND-type flash memory is to apply 0V to the word line of the selected block, float the word line of the unselected block, and apply the erase voltage to the well, thereby erasing data from the memory cells in the selected block. The erase verification determines whether the entire bit line or all the NAND strings of the selected block are qualified, and if an unqualified bit line exists, then it will be applied with the erase voltage again. Refer to Japanese Patent No. 5565948.